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1/63 AN1138 application note may 1999 the l6275 integrate into a single chip both spindle and vcm controllers as well as power stages. the device is designed for 5v disk drive application requiring up to 2.0a of spindle and 1.5 of vcm peak current. a serial port with up to 25mhz capability provides easy interface to the microprocessor. a reg- ister controlled frequency locked loop (fll) allows flexibility in setting the spindle speed. integrated bemf processing, digital masking, digital commutation delay, and sequencing minimize the number of external components required. power on reset (por) circuitry is included. upon detection of a low voltage condition, por is asserted, the internal registers are reset, and spindle power circuitry is tri- stated. the bemf is rectified providing power for the actuator retraction followed by dynamic spindle braking. the device is built in bicmos technology allowing dense digital / analog circuitry to be com- bined with a high power dmos output stage.the serial interface lines sden, sclk and sdata are 3.3v compatible. charge pump iso driver supply & clock fault monitors frequency lock loop spindle sequencer reference voltage generator 14 bit vcm dac zero cross detection a b c a+ a- a=4 supply cp fll_res fll_filter sys_clk fcom spn_comp brk_cap pwm/slew vdd por_delay porb vdd gnd dgnd v5/2 vcm_cal error_in error_out sense_out out_a out_b rsense out_c vcm_a+ vdd vcm_a- sense_in- sense_in+ vcm_gnd ctap cs sw1 sdata sclk sden clk_mon tr_5v isense index thermal dac vcm calibration bemf rectification parking vcm current control psm / lin start-up re_sync dynamic / reverse brake spindle current control pwm / lin bemf processing serial interface registers by carlo vertemara l6275 5v disk drive power combo ic
AN1138 application note 2/63 index of chapters chapter 1.0: features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 chapter 2.0: auxiliary circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 supply monitors and power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 thermal warning / shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 charge-pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4 system clock watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 chapter 3.0: serial interface circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 serial port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 registers map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3 status and identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 chapter 4.0: spindle circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1 start-up description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 4.1.1 internal start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 4.1.2 external start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 4.1.2.1 align & go . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1.2.2 stepping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1.2.3 inductive sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1.3 resynchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 4.1.4 motor stuck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 4.2 brake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2.1 three phase brake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 4.2.2 reverse brake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 4.3 current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3.1 current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 4.3.2 linear current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4.3.2.1 transconductance loop stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3.2.2 slew rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3.3 pwm current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 4.3.3.1 constant off time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.3.3.2 minimum on time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.3.3.3 slew rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.3.3.4 pwm design methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.4 speed control (fll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.4.1 internal frequency feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 4.4.2 external frequency feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 4.4.3 speed loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 4.5 bemf detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.6 delay, commutation & mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.7 fcom signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.8 bemf rectification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.9 power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.10 external isofet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.11 external bemf processing option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.12 external speed control option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3/63 AN1138 application note chapter 5.0: voice coil circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2 current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2.1 linear control loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 5.2.2 psm control loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 5.2.3 d/a converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 5.3 retract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.4 offset calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.5 power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 chapter 6.0: application & tools. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1 application configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.2 typical application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.3 smart power development system (spds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.3.1 spds hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 6.3.1.1 interface board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 0 6.3.1.2 application board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.3.2 spds software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 chapter 7.0: package & thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.1 tqfp44 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.3 slug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 chapter 8.0: appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.1 models & mathcad analisys. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.1.1 spindle current control loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 8.1.2 spindle speed control loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 8.1.3 voice coil current control loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 8.2 state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 8.3 inductive sense start-up step by step . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
AN1138 application note 4/63 index of figures figure 1: serial port write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 2: serial port read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 3: internal align & go auto start-up profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 4: inductive sense flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 5 figure 5: resynchronization timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 6 figure 6: spindle linear current control loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 7: spindle linear current loop bode diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 8: spindle pwm current control loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 9: fll counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 10: fll loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 11: bemf amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 12: internal signals timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 13: voice coil linear control loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 figure 14: voice coil psm control loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 15: voice coil psm output voltages & current signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 figure 16: power off sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 17: voice coil offset calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 5 figure 18: stand alone application configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 figure 19: external bemf processing configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 20: external speed control configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 21: external bemf processing & speed control configuration . . . . . . . . . . . . . . . . . . . . . . .38 figure 22: typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 23: smart power development system setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 figure 24: spds interface board memory address, dip switch setting . . . . . . . . . . . . . . . . . . . . . .40 figure 25: spds interface board, connectors and jumpers location . . . . . . . . . . . . . . . . . . . . . . .41 figure 26: spds application board, connectors and jumpers location . . . . . . . . . . . . . . . . . . . . . .42 figure 27: spds software realtime frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 figure 28: tqfp44 dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 figure 29: equivalent thermal circuit simplified package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 figure 30: tqfp with slug, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 figure 31: raccomended pattern for slug soldering to pcb . . . . . . . . . . . . . . . . . . . . . . . . .47 figure 32: tqfp slug design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 7 figure 33: ic temperature crise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 34: spindle current control loop model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 figure 35a: mathcad analisys of the spindle current control loop . . . . . . . . . . . . . . . . . . . . . . . . .49 figure 35b: mathcad analisys of the spindle current control loop. . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 35c: mathcad analisys of the spindle current control loop . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 36: spindle speed control loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 figure 37a: mathcad analisys of the spindle speed control loop . . . . . . . . . . . . . . . . . . . . . . . . . .53 figure 37b: mathcad analisys of the spindle speed control loop . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 37c: mathcad analisys of the spindle speed control loop. . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 38: voice coil current control loop model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 figure 39a: mathcad analisys of the voice coil current loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 figure 39b: mathcad analisys of the voice coil current loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 39c: mathcad analisys of the voice coil current loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 40: spindle motor controller state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
5/63 AN1138 application note index of tables & equation s equation 1: por delay capacitor (nf). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 1: register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 equation 2: internal start-up align time - ta (ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 equation 3: internal start-up increment time - ti (ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 2: spindle inductive sense current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 equation 4: spindle inductive sense maximum coil current (amp) . . . . . . . . . . . . . . . . . . . . . . . . . 14 equation 5: spindle resyncronization time - tsync (ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 equation 6: spindle motor stuck time - tstuck (ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 equation 7: spindle brake capacitor ( m f) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 3: zero crossing time after reverse brake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 4: spindle rsense voltage limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 equation 8: spindle maximum coil current (amp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 equation 9: spindle output slew rate resistror - rslew ( w ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 equation 10: spindle pwm constant off time - toff ( m s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 5: spindle pwm minimum on time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 equation 11: fll coarse counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 equation 12: fll fine counter] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 6: fcom output signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 equation 13: vcm loop transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 equation 14: vcm loop bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 equation 15: vcm loop low frequency gain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 7: vcm retract voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 8: vcm retract time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 equation 16: junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
AN1138 application note 6/63 1.0 features - general n 5v (+/- 10%) operation. n register based architecture n minimum external components n bicmos + vertical dmos technology (1.5 m m) - vcm driver n 1.5a drive capability n 0.9 w total bridge impedance at 25 c n linear mode n phase shift modulation (psm mode) n instantaneous, (glitch free) switch between the two modes. n class ab output drivers n zero crossover distortion n 14 bit dac define output current n selectable transconductance n 4 programmable retract voltage n dynamic brake - spindle driver n 2.0a drive capability n 0.8 w total bridge impedance at 25 c n bemf, internal / external, processing, sensor-less motor commutation n programmable commutation delay n linear mode and constant toff pwm operation mode n internal frequency locked loop speed control (fll) n bemf rectification during retract n resynchronization n built-in align & go start up n inductive sense start up option n dynamic & reverse brake n programmable output slew rate - other functions n 5v monitoring with external set trip points and hysteresis n power up/down sequencing n low voltage sense n 3.3v input logic compatibility n thermal shutdown and pre-thermal warning n system clock watchdog
7/63 AN1138 application note 2.0 auxiliary circuits 2.1 supply monitors and power-on reset the power supply monitor pin, tr_5v (#35), monitors the main supply vdd by means of external resistor di- viders. the threshold of the comparators is set internally by the band-gap reference (2v) and hysteresis is 100mv. the ratio of the external resistors set the rising trip point. at power-up, porb output pin (#34) remain low until the por delay capacitor at por_delay pin (#36) is charged. it goes low whenever either monitor input goes below the threshold . if power returns to normal during a retract sequence, the retract will finish before the por delay can begin, which means that the porb (pin #34) output will remain low until the end of the retract plus the porb delay time. for por_delay, the charge current is 2 m a and the threshold is 3v. por delay ca- pacitor is calculated as follow: ? 1. por delay capacitor (nf) example with por delay time=150milli seconds : . the bits required for vcm parking are not reset by porb and they must be always written (reg #5.3, reg #8.2 and reg #9.0.1.3.6). all the other bits are reset whenever porb is low. as long as porb is low the spindle outputs are in brake by means of turning on the low side dmos. in case of power down with the spindle pre- viously spinning, at the falling edge of porb, the spindle outputs tristate for bemf rectification and the voice coil initiate the retract phase according to the time and voltage set. after the retract time, the spindle outputs brake. the complete power off sequence is depicted in figure #16 in chapter 5 (voice coil circuit), section 5.3 (retract) 2.2 thermal warning / shutdown the thermal warning/shutdown circuit senses the temperature of the die. when the temperature reaches the thermal warning threshold, the thermal_warn bit will be reset (=0). if the temperature rises to 25 c higher than the thermal warning threshold, then thermal bit will be reset (=0). at this time, the spindle outputs are tristated and voice coil will retract. after retract, also voice coil outputs will be tristated. the registers are not reset by thermal shutdown. the spindle and vcm will be tristated as long as the internal thermal shutdown signal is active. to release this signal, the die temperature has to decrease and run bit (reg #2.3) or vcm_en bit (reg #9.5) has to be toggled. the thermal has approximately 60 c of hysteresis, so that the thermal bit will not return to normal until the chip has cool to 60 c below the rising thermal trip point. (thermal and thermal_warn are in reg #7.0.1). 2.3 charge-pump two external pins (cp pin 23, cs pin 24) are used. the base of a pnp transistor is connected to cs pin, the collector of the transistor is connected through a diode to cp pin. a storage capacitor is connected from cp to ground. an inductor whit a resistor in series is connected between vdd and the collector of the transistor. the voltage at the cp pin is called vboost. an internal oscillator is running at 200khz. this can be checked at cs pin. the vboost voltage is typical vdd+5.7v. it is possible to stop the oscillator by setting the vb/dis bit (reg#10.7). however these are used mainly for testing purpose. the internal oscillator is not stopped by por condition and it is keeping running for all the retract time as long as the vdd is greater than 2v. the current that cp pin requires is about 3ma with both spindle and vcm in linear mode operation and it is about 5ma with spindle and vcm in pwm mode operation. time 1.5 6 10 -------------------- capacitor 150 3 C 10 1.5 6 10 ------------------------ 100nf ==
AN1138 application note 8/63 2.4 system clock watchdog the device monitors the system clock frequency throughout pin #40 (clk_mon). a 15pf capacitor is con- nected between sys_clk pin (#15) and clk_mon pin. a 10k w resistor goes from clk_mon pin to ground. in the operating condition, a maximum time of 10 m s +/- 30% is allowed between sys_clk edges (rise and fall). if no edge is detected within this time the system will cause a por. to disable the system clock watchdog function, simply do not connectect any components to clk_mon pin ( #40). 3.0 serial interface circuits 3.1 serial port the the serial port interface is used to program the internal registers in addition to interfacing with the status and id registers. the serial port is enabled for data transfer when the serial data enable pin (sden pin #16) is high (=1). sden must be asserted high prior to any transmission and it should remain high until the completion of the transfer. at the end of each transfer sden should be brought low (=0). when sden is high, the data presented to the serial data pin (sdata pin #17) will be latched on each rising edge of the serial clock pin (sclk pin #18). rising edges of sclk should only occur when the desired bit of address or data is being presented on the serial data line. the data is latched into the internal register after the 16th rising edge of sclk. each transmission consists of a write control bit followed by a 7 bit address word and 8 bit data word. the address bits select the internal register to be written. the address and data fields are input lsb first, msb last, where lsb is defined as bit zero. when the write control bit is 1, the contents of the read register that is being addressed will be shifted out on the sdata pin lsb first (positive sclk edge). the sdata pin will switch from input (high z) to driving output after the falling edge of the 8th sclk pulse. all write bits in the registers are reset whenever porb is low except for retract time reg#9.3.6 and retract voltage reg#9.0.1 which must be set or reset by the external controller soon after power-up to insure that the correct value will be programmed in case of a power down situation. even though the reg#8.2 bit is not used, it must be also reset (=0) by the external controller. the serial interface is 3.3v compatible. figure 1. serial port write timing figure 2. serial port read timing 0a0a1a6 d0 d1 d7 sclk sdata sden serial port write timing 1st byte 2nd byte d2 1a0a1a6 d0 d1 d7 sclk sdata sden serial port read timing 1st byte 2nd byte d2
9/63 AN1138 application note 3.2 registers map table 1. register map reg#0: bit0~bit5, d8~d13 of vcm dac bit6, 1 vcm psm mode, 0 vcm linear mode bit7, 1 vcm calibration reg#1: bit0~bit7, d0~d7 of vcm dac reg#2: bit0, 0 to 1 transition increments spindle sequencer bit1, 1 spindle internal align & go start-up, 0 spindle external start-up bit2, 1 resets spindle sequencer to phase 1 (a -b) bit3, 1 starts spindle align & go start-up, 0 resets control logic and brakes the spindle bit4, 1 enables spindle outputs, 0 disables spindle outputs bit5, 1 electrical cycle for spindle fll control, 0 mechanical cycle for fll control bit6, 1 spindle pwm mode, 0 spindle linear mode bit7, 1 external spindle loop feedback (via index pin), 0 internal spindle loop feedback reg#3: bit0, 1 7.5 spindle mask time, 0 15 spindle mask time reg. description bit 7 bit 6 bit 5 bit 4 bit3 bit 2 bit 1 bit 0 address 0 vcm dac high byte vcm _cal psm/ lin vdac bit13 vdac bit12 vdac bit11 vdac bit10 vdac bit9 vdac bit8 0eh 00001110 1 vcm dac low byte vdac bit7 vdac bit6 vdac bit5 vdac bit4 vdac bit3 vdac bit2 vdac bit1 vdac bit0 1eh 00011110 2 spindle control ext/ int pwm/ lin mech/ elec spin_e n run r_se q start _up incre _seq 2eh 00101110 3 spindle delay sd0 sd1 sd2 sd3 8_12_ pole min1 min2 mask _time 3eh 00111110 4 fll coarse counter c11 c10 c9 c8 c7 c6 c5 c4 4eh 01001110 5 coarse/fine counter c3 c2 c1 c0 set 0 f10 f9 f8 5eh 01011110 6 fll fine counter f7 f6 f5 f4 f3 f2 f1 f0 6eh 01101110 7 spindle status go align error _lock mask _time fault rotor_ stuck thermal _warn therma l 7fh 01111111 8 spindle fll cph cpl il0 il1 isns set 0 icp sslew 8eh 10001110 9 system control retract rt1 vcm_en double rt0 vr pkv_2 pkv_1 9eh 10011110 10 test control vb/dis set 0 rev_ brake fll_out set 0 set 0 set 0 set 0 aeh 10101110 11 vcm control set 0 brake tristate set 0 com slew sleep vcmh vcms beh 10111110 12 chip id id_ rev_7 id_ rev_6 id_ rev_5 id_ rev_4 id_ rev_3 id_ rev_2 id_ rev_1 id_ rev_0 ffh 11111111
AN1138 application note 10/63 bit1~bit2, spindle pwm mode minimum on time bit3, 1 8 pole spindle motor, 0 12 pole spindle motor bit4~bit7, spindle commutation delay control sd0....sd3 reg#4: bit0~bit7, spindle fll coarse counter c4...c11 reg#5: bit0~bit2, spindle fll fine counter f8...f10 bit3, 1 spindle two phase brake ((*)only l6254), 0 spindle three phase brake bit4~bit7, spindle fll coarse counter c0...c3 reg#6: bit0~bit7, spindle fll fine counter f0...f7 reg#7: read only register bit0, 0 thermal shutdown ( >= 160 c) bit1, 0 thermal warning ( >= 125 c) bit2, 0 spindle bemf not detected bit3, 1 rapid deceleration of the spindle motor or high frequency on fcom signal. bit4, spindle mask time signal, 0 spindle bemf is masked bit5, 0 spindle speed lock error (>16 m s/sample) bit6, 0 spindle is in the internal start-up align phase bit7, 0 spindle is in the internal start-up go phase reg#8: bit0, spindle pwm (chopping) slew rate,1 20v/ m s, 0 10v/ m s bit1, charge pump current in spindle fll loop, 1 25 m a, 0 100 m a bit3, 1 presets spindle inductive sense start-up circuits bit4~bit5, spindle start-up current limitation bit6, 1 forces spindle fll charge pump low bit7, 1 forces spindle fll charge pump high reg#9: bit0~bit1, vcm retract voltage bit2, 1 connects the voltage reference (2v) for vcm calibration bit3~bit6, vcm retract time bit4, 1 doubles the times for the internal spindle align and go start-up bit5, 1 enables vcm bit7, 1 initiates the vcm retract reg#10: bit4, 1 spindle mechanical or electrical output, 0 spindle zero cross output bit5, 1 spindle reverse brake bit7, 1 disables vboost reg#11: bit0, vcm psm (chopping) slew rate,1 20v/ m s, 0 10v/ m s bit1, 1 forces vcm outputs to be high in psm mode bit2, 1 unused (future power saving mode) bit3, 1 spindle pwm (phase commutation) slew rate 1 2v/ m s, 0 30v/ m s reg#12: read only register bit0~bit7, for chip id 3.3 status and identification registers the status register (reg#7) and the identification register (reg#12) are read only registers, while all the oth- ers are only write registers. the status register provides informations of the spindle motor (bits 2...7) and the thermal behaviour of the device (bits 1,2). n thermal - bit #0. normally is set to 1, when the junction temperature reaches about 160 c, the bit will be set to 0. this will automatically tristate the spindle outputs and the voice coil will initiate the
11/63 AN1138 application note retract.the bit will return to normal when the temperature will drop about 60 c. all the functions of the device but the reading in the serial port, will be in stand-by as long as this bit is set to 0. n thermal_warn - bit #1. normally is set to 1, when the junction temperature reaches about 125 c, the bit will be set to 0. the device will take no action upon this bit set to 0. corrections are demanded to the m p. this bit will return automatically to normal (=1) when the temperature will drop below the set point (about 125 c). n rotor_stuck - bit #2. normally is set to 1, if the spindle bemf is not detected, the bit will be set to 0. this can happen for example during start-up because the spindle motor may be stucked. the device will tristate the spindle and vcm outputs upon this bit is set to 0. n fault - bit #3. normally is set to 0, if the spindle motor decelerate rapidly or the fcom signal change to high frequency, the bit will be set to 1. the device will take no action upon this bit set to 0. corrections are demanded to the m p. n mask_time - bit #4. by reading continuosly this bit, the internal bemf mask time signal can be monitored. when the bit is 0, the bemf is masked. n error_lock - bit #5. when the spindle speed is at target speed +/- 16 m s sample, the bit will be set to 1, otherwise will be set to 0. n align - bit #6. normally is set to 1, when the spindle motor is in the align phase of the internal align&go start-up, the bit will be set to 0. n go - bit #7. normally is set to 1, when the spindle motor is in the go phase of the internal align&go start-up, the bit will be set to 0. by reading and decoding the identification register , the revision of the device can be retrieved.
AN1138 application note 12/63 4.0 spindle circuits 4.1 start-up description the spindle driver has the ability to stand alone start-up the motor using an internal align & go algorithm. al- though the internal start-up will spin-up the motor consistently, the possibility exist where certain applications might require complete microprocessor control. in this case, the chip provides all the function and signals to ex- ternally build a custom start-up. 4.1.1 internal start-up the internal start-up is asserted by setting (=1) the start_up bit (reg#2.1). assuming that the motor is sta- tionary, when run and spin_en bits (reg#2.3.4) are set (=1), after a resynchronization time, the motor will be in align mode with phase 1 active (output a high and output b low. please note that this output configuration is true at power on condition or whenever reset sequencer is asserted, by toggling the r_seq bit (reg#2.2), oth- erwise can be different). after a ta time (align time) the sequencer double increments the outputs to phase 3 (output b high and output c low). after a ti time (increment time) the sequencer double increments again the outputs and the controller enters the go mode, with the sequencer automatically incrementing the output phase upon detection of the motors bemf. the times labeled ta and ti are two delays that are 25% and 75% respec- tively of the total delay time and they are determined by the frequency of the system clock signal present on pin#15, (sys_clk). by setting the double bit (reg#9.4), ta and ti can be doubled. ta and ti are calculated as formula #2 and #3. the figure#3 depicts the internal align & go auto start-up profile. figure 3. internal align & go auto start-up profile spin_en run sequencer phase 1 phase 2 phase 3 phase 4 phase 5 ta ti align go output phase alignament go ta tgo
13/63 AN1138 application note ? 2. internal start-up align time - ta (ms) ? 3. internal start-up increment time - ti (ms) example with 20mhz sys_clk and double=0: 4.1.2 external start-up when the start_up bit (reg#2.1) is reset (=0) the internal auto-startup algorithm is disabled and the se- quencer is accessible allowing the microprocessor to control the phase commutation of the motor. the chip of- fers this capability via the incre_seq bit (reg#2.0). the transition 0 to 1 of this bit increments the sequencer to the next position. a feedback from the motor (zero cross) is available on pin #1, fcom. fcom toggles at each successive zero crossing and it can be monitored to assure that motion occurred. with this approach the microprocessor or dsp can access all the function of the chip and different start-up algorithm can be applied to spin-up the motor. following are three start-up algorithm examples: align & go , stepping and inductive sense . 4.1.2.1 align & go the external align & go start-up is structured as the internal one. the times ta and ti along with the com- mutation must be provided externally by the m p allowing further flexibility to the system. assuming that the motor is stationary, when run and spin_en bits (reg#2.3.4) are set (=1), the motor is in align mode with phase 1 active (output a high and output b low, please note that this output configuration is true at power on condition or whenever reset sequencer is asserted, by toggling the r_seq bit (reg#2.2), otherwise can be different). af- ter a ta time (align time handled by external m p) the sequencer can be double incremented to phase 3 (output b high and output c low) by toggling the incre_seq bit (reg#2.0). after a ti time (increment time) the se- quencer can be double incremented again which should produce torque in the desired direction. a little waiting time greater than the length of the recirculation spike produced by the motor coil during commutation (typical 3 m s) must be applied prior the end-over operation. at this time, by setting the start_up bit (reg#2.1), the sequencer is controlled by the bemf zero crossing and the motor should ramp up to speed. 4.1.2.2 stepping this approach is driven in a similar fashion to a stepper motor. the start_up bit (reg#2.1) must be reset (=0), run and spin_en bits (reg#2.3.4) must be set=1. by toggling the incre_seq bit (reg#2.0), the com- mutation rate is continually increased until the bemf voltage is large enough to reliably use the zero-crossing for commutation timing. once this point has been reached, a little waiting time greater than the length of the recirculation spike produced by the motors coil during commutation (typical 3 m s) must be applied. by setting the start_up bit (reg#2.1), the bemf zero crossing will automatically control the sequencer and the motor control circuit will take over to bring the motor into frequency lock. the stepping approach takes longer than other start-up algorithm because the initial commutation frequency and subsequent ramp rate must be low enough so that the motor can follow without slipping. this implies that to have a reliable algorithm, the initial frequency and ramp must be carefully calculated according to the mechanical and electrical motor characteris- tics and under worst case conditions. 2.56 6 10 sys_clk ----------------------- ? ?? 1double + () 7.68 6 10 sys_clk ----------------------- ? ?? 1double + () ta 2.56 6 10 20 6 10 ----------------------- ? ? ?? 10 + () 128ms - ti 7.68 6 10 20 6 10 ----------------------- ? ? ?? 10 + () 384ms ====
AN1138 application note 14/63 4.1.2.3 inductive sense since hard drive heads are not designed for back rotation, it is important to know which spindle phase should be energized first, in order to avoid back-rotation. during operation, the electrical phase of the motor can be detected by sensing the bemf induced in the unen- ergized winding by the rotors magnet in motion, however, when the motor is stopped, detection of the rotor po- sition is more difficult. for this purpose, the inductive sense algorithm has been developed. to get the position of a stopped three phase permanent magnet rotor, the inductance of each of the six motor commutation phases is sensed by applying a voltage across each combination of two motor winding and measuring the time required for the current through the windings to reach a certain arbitrary selected value. the shortest rise time should correspond to the lowest inductance and this commutation phase should be the one closest to the mechanical position of the rotor. altought no inductive sense algorithm is built inside the device, it provides all the hardware functions that inter- acting with the m p can externally perform the inductive sense start-up. the isns bit (reg#8.3) must first be set (=1) in order to preset the internal circuit to sense the current in the coils. this allow the fcom pin (#1) to become the information signal of threshold reached. there are four different threshold values which adjust the maximum voltage on sense resistor. the threshold can be selected by changing the il0 and il1 bit in the reg#8.4.5. the table #2 shows the available values. table 2. spindle inductive sense current limit the current that flow into the coil is also a function of the sense resistor connected to the rsense pin and it is calculated as follow: ? 4. spindle inductive sense maximum coil current (amp) example with rsense=0.3 w and il0/il1/isns=1 : max coil current = (0.3 / 0.3) = 1 a. figure#4 shows the flow chart of the inductive sense start-up routine. a step by step procedure to build the inductive sense start-up, can be found in chapter 8 (appendix), section 8.3 (inductive sense start-up step by step). il0 il1 isns v_sense_limit (+/- 15%) 00 1 .15v 10 1 .20v 01 1 .25v 11 1 .30v v_sense_limit rsense ------------------------------------------
15/63 AN1138 application note figure 4. inductive sense flow chart hardware initialization set threshold set phase= 1 set trial=1 store initial time period provide current to coils accordin g to phase and start counter threshold reached ? stop counter read counter ground coil stop counter lower threshold no yes no begin is time g reater than 50ms ? store time store phase ground coils yes is time < stored time ? no yes get the phase with a most frequent shortest time increment phase store phase with lowest time trial=5 ? yes phase=6 ? increment trial set phase=1 no no yes raise start-up current threshold phase increment ali g nament time phase increment mask time hardware zero cross detection end brin g the sequencer to the phase detected
AN1138 application note 16/63 4.1.3 resynchronization the resynchronization is the ability to spin-up the motor without going through the start-up routine when the power is momentarily lost with the motor still moving and bemf is detected. supposing that the spindle is run- ning at a certain speed, when a por (power on reset) occurs, the spindle outputs are tristated and the motor will coast. if the power come back, porb high, the internal circuit will first check for the bemf and if some con- secutive zero cross are detected, the system will be able to resynchronize the sequencer and get the motor at speed again. please note that when por condition occurs, most of the internal registers are reset, for this rea- son, it is important to restore the desired bits value as fast as possible upon por gets back. also note that the porb stays at low level until por delay time expire. the spindle resynchronization circuit stand-by for the bemf (zero cross transition) for a tsync time, which it is calculated as follow: ? 5. spindle resyncronization time - tsync (ms) example with 20mhz sys_clk : . the number of consecutive zero cross that the chip needs to detect before resynchronizing depends from the instant that the system is activated (porb high and reg#2.1.3.4 =1), after for example a glitch in the power supply. the first valid zero cross, as it is shown in figure #5, is set in point #1 (phase a-b, this is true right afer por goes on or whenever r_seq bit (reg#2.2) is toggled). the points (zero crosses) between the system activation and the resynchronization point (point #2) are the number of zero cross that the system has to de- tect, therefore the time before the resynchronization can initiate. if the motor is coasting and the chip is activated between point 1 and 2, the number of zero cross necessary will be 7. if the chip will be activated between point 6 and 1 the chip will resynchronize after two zero crosses. if the spindle outputs are disabled by resetting (=0) the spin_en bit (reg#2.4), while the motor was spinning, the system will keep track of the zero crosses and it will resynchronize at the next zero cross upon the spin_en bit is re-asserted. figure 5. resynchronization timing after start_up, run and spin_en bits are set (reg#2.1.3.4=1), the system is halted waiting for a zero cross to occur within a tsync time as explained before. if not enough zero crosses are detected, after tsync time, the internal align&go algorithm is initied. if another start-up is required (i.e. inductive sense), it is man- datory to reset the spin_en bit before the end of the resynchronization time in order to avoid the internal start- up to be initiated. in other word, the external m p, in parallel with the chip, needs to keep track the time and 8.4 6 10 sys_clk -------------------------- - tsync 8.4 6 10 20 6 10 -------------------- ? ? ?? = 420ms = phase a phase b phase c a-b a-c b-c b-a c-a c-b a-b a-c b-c resynchronization 2 3 5 4 1 6 1 2 3 resynchronization first valid z.c. first valid z.c.
17/63 AN1138 application note the bemf (looking at fcom pin (#1)) and take action whether internal or external start-up is to be ini- tiated. if the motor is spinning and enough zero cross are detected, no actions are required, the chip sequenc- er will automatically lock on to the proper phase and bring the motor speed up to frequency lock. 4.1.4 motor stuck the purpose of this feature is to protect the motor and the circuits against an over-heating due to high current in the same phase when the motor is not moving. during start-up, when a phase is energized according to the sequencer in the go phase, the current starts to flow into the motor winding producing a torque which should result a mechanical movement of the rotor to the next position. if for some reason the rotor does not move (not enough torque or the motor is stuck) and the bemf is not detected within tstuck time, the system will shut off the current in the spindle tristating the outputs and the controller will enter the stuck rotor hold state. to re- sume from this condition, run bit (reg#2,3) must be toggled. following is the formula to calculate the tstuck time. ? 6. spindle motor stuck time - tstuck (ms) example with 20mhz sys_clk: the above description is valid always and not only at start-up. this means that the stuck rotor counter is active all the time, also when the motor is running at steady speed. if for some reason, which it is, of coarse unlikely to happens (unless the speed gets extremely low such as tzero_cross > tstuck), the bemf is not detected within tstuck time, the stuck rotor circuit will react as explained before. the stuck rotor information can be read as a 0 in the reg#7.2. 4.2 brake the brake is the ability to completely stop a spindle motor in a reasonable time. there are two different way to stop the spindle motor, one is commanded through the serial port and the other one is when the power supply is turned off causing a por condition. the device offers three different mode to brake, three phase brake and reverse brake . in a power-down condition only three phase brake are available. 4.2.1 three phase brake the brake function is asserted by resetting (=0) the run bit (reg#2.3) in power on condition and after retract in case of power loss. the low side output dmos of phase a, b and c at this time are turned on. in a power-down condition, after retract, when spindle brake initiate, the voltage on vdd drops very rapidly be- cause the low side dmos are turned on shorting the motor bemf. in order to keep the spindle sink transistors on in this mode, an external capacitor is used on the brk_cap pin (#12) to hold the gates of the sink devices on. this capacitor is charged up whenever vdd is high to about 5v, and it is isolated from all supplies by block- ing diodes. following is the formula to calculate brake storage capacitor where time is the duration in seconds of the brake time required. ? 7. spindle brake capacitor ( m f) example with brake time=8 seconds : . 4.2.2 reverse brake it is available only when power is present (porb=1). it is asserted by setting the rev_brake bit (reg #10.5). 8.4 6 10 sys_clk --------------------- - tstuck 8.4 6 10 20 6 10 -------------------- ? ? ?? 420ms == 25 8 C 10 time brake capcitor 25 8 C 10 8 () = 2 m f =
AN1138 application note 18/63 at this time the current in the winding of the motor is reversed respect its previous flowing, resulting a rapid de- celeration of the motor. the system will end over to the normal three/two phase brake (according to the reg#5.3 bit value) as soon as the time between two zero cross is reaching a predefined value. three different values are available by toggling the rev_brake bit (reg#10.5) according to the following table (#3). table 3. zero crossing time after reverse brake since the saturation of the powers are required to succeed the reverse brake operation, the above statement is valid if pwm current control mode is operating. in case of linear control loop, a little trick needs to be used. right before setting the rev_brake bit , the cph bit (reg#8.7) must be set (=1). this will disconnect the fll loop from the current control loop bringing quickly the low side dmos to saturation. 4.3 current control the current in the spindle motor is sensed by a small resistor (typ. 0.3 w ) connected to the bottom of the h bridge and ground. the voltage drop across the resistor is amplified by a sense amplifier with a gain of four. the output voltage of the sense amplifier is sent to the error amplifier stage where it is compared to the current command coming from the fll circuit. the error amplifier circuit will drive the power stage according to the driving mode selected. the device provides two different current control loop, linear and pulse width modulation (pwm). by changing the reg#2.6 bit, the selection of the two modes can be done any time regardless the motor is run- ning or not. 4.3.1 current limitation during initial start-up, the error signal from the output of the fll will be at compliance in order to quickly bring the motor up to correct speed. the maximum current flowing into the coil at the beginning (when the motor is stopped and no bemf is present) is given by the following equation where rdson is the on resistance of the power dmos. icoil = vsupply / (2*rdson + rmotor + rsense ) the motor current during this condition can be safely limited to a predetermined value by setting the appropriate bits il0 and il1 (reg#8.4.5) according to the table #4. table 4. spindle rsense voltage limit reg#10.5 zero cross time 1 toggle 10ms 2 toggles 20ms 3 toggles 40ms il0 il1 v_sense_limit (+/- 15%) 0 0 .45v 1 0 .50v 0 1 .55v 1 1 .75v
19/63 AN1138 application note the current flowing into the coil will be calculated as follow: ? 8. spindle maximum coil current (amp) example with rsense=0.3 w and il0/il1=0 : max coil current = (0.45 / 0.3) = 1.5 a. 4.3.2 linear current control the linear mode of operation for the spindle driver is activated by a 0 on bit 6 in the spindle control register reg #2.6. figure 6. spindle linear current control loop the output current is controlled in a linear fashion via a transconductance loop. referring to figure #6, the sourcing fet (high side dmos) of one phase is forced into full conduction, while the sinking fet (low side dmos) of an appropriate phase operate as a transconductance element. during a run condition, the current in the sinking fet, is monitored by a rsense resistor. the resulting voltage that appears across the resistor is amplified by a factor of four by the sense amplifier opamp and is sent to the error amplifier stage where it is compared to the current command coming from the fll circuit. the error amplifier circuit along with the buffer, provides sufficient drive to the sinking fet in order to maintain the motor speed at the proper level as command- ed by the speed controller (fll). v_sense_limit rsense ------------------------------------ - rsense rc cc g g=4 + - spindle motor ota rsense isense spn_comp power stage vdd fll vdd current sense stage error amplifier stage buffer sequencer sense opamp low side a c b high side pin#44 pin#5 pins#13,43 pins#6,9
AN1138 application note 20/63 4.3.2.1 transconductance loop stability the rc network connected to the compensation pin (spin_comp pin#44 - figure #6) provides a single pole/ zero compensation scheme. the pole/zero locations are adjusted such that a few db (typ. 20db) remains in the transconductance loop at frequencies higher than the zero. the inductive characteristic of the load provides the pole necessary for loop stability. thus the loop bandwidth is actually limited by the motor itself. figure 7. spindle linear current loop bode diagram the bode plot in figure #7, depicts the normal way to achieve stability in the loop. the pole and the zero are used to set a gain of 20db at a higher frequency and the pole of the motor cuts the gain to achieve stability. loop instability may be caused by two factor: 1) the motor pole is too close to zero. the zero is not able to decrement the shift of the phase, and when the effect of the motor pole is present, the phase shift may reach 180 and the loop will oscillate. to rectify this situation the pole/zero must be shifted at lower frequencies by increasing the compensation capacitor (cc). 2) the motor capacitance itself can interfere with the loop, creating double poles. if the gain at higher frequen- cies is sufficiently high, the double pole slope of 40db/decade can cause the phase shift to reach 180 , re- sulting in oscillation. by leaving the pole unchanged and increasing the zero, the stable response can be achieved. the model and a mathcad analysis for the spindle current control loop can be found in chapter 8 (appendix), section 8.1.1 (spindle current control loop). 4.3.2.2 slew rate control a 3-phase motor appears as an inductive load to the power supply. the power supply sees a disturbance when one motor phase turns off and another turns on because the dmos turn-off time is much shorter than the l/r rise time. furthermore, the turn-off of the dmos can even cause current recirculation back into the supply. however, the need for a snubber circuit can be eliminated by controlling the turn-off time of the dmos. the rate at which the upper and lower drivers turn on and off is programmable via an external resistor, rslew, connected to the pwm/slew pin (#3). this resistor define an internal current source that is utilized to limit the voltage slew rate at the outputs during transition, thus minimizing the load change that the power supply sees. frequency av rocc rccc motor pole 20db ro = ota output impedance
21/63 AN1138 application note to insure proper operation, the range of the resistor value indicated should not be exceeded. if a relatively low value of rslew is selected, the resultant fast slew rate will result in increasing commutation cross-over current, higher emi and large amount of commutation current. higher values of rslew result of course in slow slew rate at the outputs which is, under most conditions, the desired case since the problems associated with fast rates are reduced. the additional advantage is lower acoustical noise. problems can occur though if the slew rate for a given application is too slow. the problem manifest itself as the motor begins to spin-up. at lower rpms, the bemf of the motor is relatively small resulting in higher amounts of commutation current. the excessively long slew rate may exceed the mask period and the commutation spike can be detected as a zero cross. with a high value of rslew, also the power dissipation needs to be considered. following is the formula to cal- culate the intended slew rate resistor in linear mode. ? 9. spindle output slew rate resistror - rslew ( w ) example for slew rate = 6v/ m s : 4.3.3 pwm current control the pwm mode of operation for the spindle driver is activated by a 1 on the spindle control register reg #2.6 bit. in the switch mode current control operation, only the high side drivers are pulse width modulated to control the current in the motor. the low side drivers are fully switched on or off according to their commutation se- quence timing. the pwm control of the high side drivers is achieved by a constant toff single shot circuit. constant toff control operates on the principle of monitoring the motor current and comparing it to a reference or control level (fll). when the motor current reaches this commanded level, the output drivers turn off and remain off for a constant time. after this time the drivers turn back on to repeat the cycle. referring to figure #8, the current in the motor windings is monitored via the voltage dropped in the sensing resistor, rsense. this voltage is multiplied by a factor of four in the current sense amplifier and sent to the negative input of a com- parator. the control voltage (fll), is applied to the positive input of the comparator. when the output of the current sense amplifier reaches a level that is equal to the commanded level, the output of the comparator switches low resetting the q output of the f/f. this causes the upper driver to turn off and through -q (which will go high) turn off the pmos switch allowing the capacitor (coff) to discharge through roff, initiating then the constant toff time. when the voltage on coff reaches 1.2v, the f/f will be set again causing the upper drive to turn on and the coff capacitor itself to be quickly recharged. the figure #8 shows the current control loop in pwm mode. 310 4 10 () slew rate ------------------------------- rslew 310 4 10 () 6 ------------------------------- 50k w ==
AN1138 application note 22/63 figure 8. spindle pwm current control loop 4.3.3.1 constant off time the timing of the single shot circuit can be programmed by an external rc network at pwm/slew pin (#3). the constant off time can be calculated as follow: ? 10. spindle pwm constant off time - toff ( m s) example for toff = 10 m s and roff = 100k w (typ.): . 4.3.3.2 minimum on time in a spindle pwm current control system, the chopping in a commanded phase causes a swinging also in the floating phase. for this reason the bemf zero cross signal is masked most of the time. the bemf detection is possible by opening a small window in which the floating phase is monitored. the window will be opened 6.4 m s (based on 20mhz sys_clk) after the turn on of the driver and it will be closed when the zero cross occurs or at the turn off of the driver. in the case of minimum on time less than 6.4 m s, the window will be opened only at the point where the output is about to be turned off and then it will be closed right away. since the noise caused by the turning on of the high side driver can be detected as a false zero cross, the rsense g g=4 + - spindle motor rsense isense power stage fll vdd current sense stage sequencer sense opamp low side a c b high side f/f q r roff coff constant toff stage -q s 2.5v pmos switch comparator pwm/slew pin#3 pin#5 pins#6,9 vdd pins#13,43 0.69 r off c off coff 10 6 C 10 0.69 -------------------- - 100 3 10 150pf ==
23/63 AN1138 application note minimum on time has to be chosen large enough to cover those spike. in the other hand has not to be too large otherwise the motor can not slow down fast when required or it may run at higher undesired speed. for this reason four different on times value are available through the serial port, min1 and min2 bits (reg#3.1.2), those timing are not dependent from the external sys_clk signal but are internally generated. the table #5 shows the timing available. table 5. spindle pwm minimum on time 4.3.3.3 slew rate control in the pwm current control mode, two different slew rate control are present, the first one during commutation and the second one during chopping. both are addressable through the serial port. the comslew bit (reg#11.3) will performs slew rate at commutation with 0 for 30v/ m s and 1 for 2v/ m s. the sslew bit (reg#8.0) will perform slew rate during chopping with 0 for 10v/ m s and 1 for 20v/ m s. 4.3.3.4 pwm design methodology the bandwidth of the pwm loop was optimized to reject unwanted switching noise while providing sufficient re- sponse, commensurate with the switching speed of the output drivers. at higher frequencies the switching loss- es inherent in the drivers start to negate any of the power dissipation savings gained with pwm operation. at lower frequencies, less that 20khz, the switching of the coil may result in the undesirable acoustic range. a good compromised pwm frequency can be assumed around: (1) chopping frequency: 30-40khz. the time that the current flowing into an inductor needs to reach a certain value is equal to a time that it needs to get from that value to zero. this time is depending from the inductor (lm) and the resistor (rm) values. in the case of a running motor the bemf generated by the motor itself at that speed needs to be taken in consid- eration. due to the fact that bemf is opposing to the power supply, the voltage across the motor will be less (vmotor = vpower-bemf). for this reason the charging and discharging of the inductor will result with different voltage and so different duration. the ratio to have a good regulation margin will be about: (2) ton / toff ratio: ton = 70% - toff = 30% the device architecture has been designed to work in constant off time mode, this means that the system is using the frequency (changing only the on time) to adjust the speed. the ratio ton / toff provide the motor with the required amount of current to spin at desired speed. assuming that 40khz chopping frequency is used, at steady speed, the period will be equal to 25 m s. for the previous assumption (2), the toff needs to be 30% of 25 m s so will be about 7.5 m s. in this case the ton will be equal to 17.5 m s (ton=period -toff). if this ratio can not be achieved, most probably the motor is not been designed to run at that speed (bemf provided is too high). 4.4 speed control (fll) the rotational position of the motor is inferred from the bemf waveform generated by the floating coil. the chip uses the instant of a particular zero-crossing and the period between successive zero crossings to dictate the min1 min2 minimum on time 00 5.9 m s 01 1.4 m s 1 0 12.0 m s 1 1 5.21 m s
AN1138 application note 24/63 commutation timings. the complete control loop is on chip and the speed is controlled by a reference clock at pin sys_clk (pin#15). the speed control loop uses a frequency locked loop (fll) which in conjunction with an external compensation network brings the frequency of the tachometer signal to be equal to the internally generated reference frequen- cy. the tachometer signal can either be the bemf signal divided down to a once per mechanical or electrical revolution signal or an externally generated tachometer signal, sector burst. the output of the speed control is a current demand signal that goes to the spindle driver. there are a "fine" and a "coarse" counters that define the speed of the motor. the register #4 and half of the #5 are the fll coarse counter registers (12bits total, only count down to zero). the register #6 and the other half of the #5 are the fll fine counter registers (11bits, count down to 2s complement of the 11 bit value). the figure #9 shows the counters. figure 9. fll counters in more detail, those three registers are used in conjunction with two down counters which form a frequency detector that in turn creates feedback through to a charge pump to maintain the motors speed regulation. the frequency clock applied to sys_clk pin is internally divided by a factor of 5. the coarse counter is 12 bits and it is clocked at 1/64th the rate of the internal frequency clock. the fine counter is 11 bits and it is clocked at 1/4th the rate of the internal frequency clock. the on-chip frequency locked loop uses the electrical or mechanical cycle pulses, according to the reg#2.5 setting to adjust the speed of the motor. upon the first pulse, the coarse register's contents (loaded via the serial port) is loaded into the internal coarse counter which immediately starts to count down. when this coarse counter reaches zero, the fine counter is then loaded from its corresponding register. the fine counter then also immediately starts to count down. the fine counter can count down through zero and continue counting down to the 2's complement of the original fine counter value. the period between the start of the coarse counter and the zero crossing during the fine counter operation is time course counter countin g down fine counter countin g down fll course re g ister value fll fine re g ister value zero crossin g expected here desired period between zero crossin g s e.g. actual zero crossing actual error between expected zero crossin g and actual zero crossin g . this value is fed into the char g e pump to either speed up or slow down the rotation. "previous" zero crossing course counter countin g down fine counter countin g down e.g. actual zero crossing
25/63 AN1138 application note the programmed period. any differences between the desired period and the pulse is the error in the transcon- ductance loop and corrective action is taken by the charge pump. the pulse measurement is initiated by an edge of the feedback frequency (figure #10). if the feedback fre- quency is higher than the reference frequency, then a down pulse will be generated whose width is the differ- ence in pulse width of the two inputs. if the feedback frequency is lower than the reference frequency than an up pulse will be generated whose width is the difference on pulse width of the inputs. the maximum pulse width of the frequency comparator is set by the value programmed into the fine counter. up and down pulses control the output of a current source or sink respectively which are connected to the fll_filter pin (#21). the cur- rent source and sink may also be turned on by the cph and cpl bits in the serial port (reg#8.6.7), however these are mainly for testing purpose. the value of the source and sink currents is set by the icp bit (reg#8.1) in the serial port. the result of this is a current pulse, whose width is proportional to the speed error, this is pre- sented to the fll_filter pin which is used with an external rc network to construct the loop filter for the motor speed control. the fll_filter pin is also internally connected to the input of a unity gain buffer. the output of this buffer is clamped to a voltage set by ilo, il1 and isns bits (reg#8.3.4.5.) in the serial port. the value for the clamp voltage are outlined in tables #2 and #4. the coarse and fine counter arrangement is guaranteed to work in all possible circumstances. for example if the zero crossing is within or outside the fine window or even if the zero crossing is in the coarse register range. this system will even work if the zero crossing occurs across multiple coarse/fine cycles. the fll has a pres- caler (defined by the system control register bits mec/elec and 8_12_pole (reg#2.5 & reg#3.3) that changes the cycle counting mechanism between electrical or mechanical (8 pole or 12 pole) i.e. dividing the electrical period clock by 1, 4 or 6. the equation for setting the coarse and fine counters are calculated as shown in formulas #11 and #12 where t0 is the period of the updating frequency that can be either electrical or mechanical and it is calculate as t0 = 60 / rpm * cycle . cycle is the cycle counting mechanism and as explained before it can be 1,4 or 6 according to desired cycle. use 1 if mechanical cycle is selected, use 4 or 6 if electrical cycle is chosen according to the motor pole. conventionally, 90% of t0 goes into the coarse counter, 10% goes into the fine counter. rpm is the desired speed. the coarsecounterperiod is the time of one period of the coarse counter and it is equal to 1/frequen- cy(sys_clk) * 5 * 64. the finecounterperiod is the time of one period of fine counter and it is equal to 1/ frequency(sys_clk) *5 *4 . the coarsecountererror is the error from the coarse counter calculation and needs to be added to the fine register calculation. ? 11. fll coarse counter ? 12. fll fine counter] example whit a speed of 5400rpm, cycle=mechanical and sys_clk=20mhz. 1. calculate t0 reference period. t0 = 60 / (speed*cycle) = 60 / (5400 *1) = 11 ms 2. calculate coarse counter period. coarsecounterperiod = (1 / frequency(sys_clk)) *5 * 64 = (1 / 20e6) * 5 * 64 = 16 m s 3. calculate fine counter period. finecounterperiod = (1 / frequency(sys_clk)) *5 * 4 = (1 / 20e6) * 5 * 4 = 1 m s 4. calculate coarse register value. coarse_reg 0.9 t0 () coarsecounterperiod ----------------------------------------------------------------- - = coarse_freq 0.1 t0 () coarsecountererror + finecounterperiod --------------------------------------------------------------------------------------------- =
AN1138 application note 26/63 coarse_reg = (0.9 * t0) / coarsecounterperiod = (0.9 * 11e-3) / 16e-6 = 618.75 the number 618 is the value that has to be programmed into the coarse counter register. the decimal number 0.75 is the error that needs to be added to the computation of the fine register. 5. calculate coarse counter error. coarsecountererror = 0.5 * coarsecounterperiod = 0.75 * 16e-6 = 12 m s 6. calculate fine register value. fine_reg = (0.1*t0+coarsecountererror) / coarsecounterperiod = (0.1*11e-3+12e-6) / 1e-6 = 1112 the number 1112 is the value that has to be programmed into the fine counter register. figure 10. fll loop since the coarse counter is a 12 bit counter, the maximum count available is 4096. therefore, from the above example, the full coarse count set limit will be 65,536ms (4096*coarsecounterperiod). the fine counter is only a 11 bit counter for a total of 2048 counts. the full fine count set limit will be 2,048ms (2048*finecounter- period). if a greater number will result from the calculation, the percentage of t0 used in the fine counter equa- tion needs to be decreased and added to the coarse counter equations (for example , 91% of t0 goes into the coarse counter and 9% of t0 goes into the fine counter). this procedure needs to be repeated until the num- ber will fit the fine counter register. figure #10 depicts the complete fll loop block diagram. 4.4.1 internal frequency feedback the internal frequency for the speed loop feedback is taken internally from the fcom signal divided down by 3 and it is selectable by resetting (=0) the ext/int bit (reg#2.7). the figure#10 shows the configuration. %3 zero cross ext/int=0 ext/int=1 index 8/12p=0 %4 8/12p=1 %6 me/el=0 me/el=1 fre q uenc y comparator fine counter coarse counter %64 %5 %4 sys_clk tachometer sample reference frequency generator reg#2.7 reg#3.3 reg#2.5 electrical period mechanical period feedback frequency reference frequency reg#4.0:7 reg#5.4:7 reg#5.0:2 reg#6.0:7 fll_filter pin a=1 spindle ota voltage clamp il0 re g #8.5 il1 re g #8.4 isns re g #8.3 external loop filter vdd gnd icp re g #8.1 icp re g #8.1 cph re g #8.7 cpl re g #8.6 up down
27/63 AN1138 application note 4.4.2 external frequency feedback an index pin (#11) is provided for external speed loop feedback frequency. this pin will allow the user to control the motor speed with a signal taken from the data read off of the disk itself. this mode is selectable by setting (=1) the ext/int bit (reg#2.7). the figure#10 shows the configuration. 4.4.3 speed loop compensation the frequency comparator and charge pump generate and error current based on the frequency difference between a programmed reference frequency. this error current is converted to an error voltage by the loop filter, which programs the current delivered to the motor through the ota loop. the model and a mathcad analysis for the spindle speed control loop can be found in chapter 8 (appendix), section 8.1.2 (spindle speed control loop). 4.5 bemf detection since no hall effect sensors are required, the commutation information is derived from the bemf voltage zero- crossing of the undriven phase with respect to the center tap. the bemf comparator and associated signal levels are depicted in figure #11. for reliable operation, the bemf signal amplitude should be a minimum of +/- 40mv to be properly detected. in order to provide for noise immunity, internal hysteresis (typically 15mv) is incorpo- rated in the detection circuitry to prevent false zero crossing detection. figure 11. bemf amplifier 4.6 delay, commutation & mask the figure #12, represent the internal signal timing associated with the motor bemf and output stage. + - vbemf sa sb sc <= 40mv ctap out a out b out c
AN1138 application note 28/63 figure 12. internal signals timing the bemf waveform is shown as a reference along with a dashed line to indicate the occurrence of a zero crossing. a typical sequence starts when the outputs switch states. referring to figure #12, during phase 1, mask commutation delay zero cross output c output b output a 60` 15` bemf phase 1 phase 2 phase 3 phase 4 phase 5 phase 6 phase 1 phase 2 phase 3 phase 4 phase 5 phase 6 phase 1
29/63 AN1138 application note output a goes high, while output b is low. during this phase, output c is floating and the bemf is monitored. the outputs remain in this state for 60 electrical degrees as indicated by the first set of dashed lines. after this pe- riod the output switches to phase 2 with output a high and c low with the bemf amplifier monitoring output b. in order to prevent commutation current noise being detected as a false zero crossing, a masking circuit auto- matically blanks out all incoming signals as soon as a zero crossing is detected. when the next commutation occurs an internal counter starts counting down to set the time that the masking pulse remains. this time is equal to 7.5 or 15 of the electrical cycle and it can be programmed through the serial port by setting or resetting the reg#3.0. thus the actual masking period is the total of the time from the detected zero crossing to the com- mutation plus 12.5% (7.5 ) or 25% (15 ) of the previous period. the selection of the mask has to be done in order to cover (as shown in figure #12, between dashed lines) the spike produced by the commutation. this can be sperimentally achieved by looking with an oscilloscope the phase commutation voltage during start-up (worse case condition due to high current). the time of the mask signal has to be large enough to cover the duration of the commutation spike. after the masking period, the bemf voltage at output b is monitored for a zero crossing. upon detection of the zero crossing the output is commutated after a delay (in case of figure #12, 30 electrical degrees) insuring maximum torque. the delay can be programmed through the serial port by setting reg#3.4:7 bits. the adjust- ment range is from 1.875 through 30 electrical degrees in 1.875 degree increments. the delay has to be chosen in order to optimize the commutation point to insure maximum torque. this can be sperimentally achieved by looking with an oscilloscope the voltage and the current in a phase and adjusting the delay in order to have those waveforms as much symmetric as possible. 4.7 fcom signal the fcom signal available on pin#1 has two different functions. normally when the motor is running it will pro- vide feedback information of the rotors position (zero crossing, electrical or mechanical). during spindle in- ductive sense start-up, it will provide informations whether the current threshold is reached or not. in this last case, if spindle linear current control is used the fcom pin will start low and it will go high when the current in the sense resistor will reach the threshold set by il0,il1 and isns bits (reg#8.3.4.5) . the fcom pin will stay high until the spindle outputs are disabled then it will go low again. if spindle pwm current control is used, the fcom will behave like in linear mode but instead to stay all the time high, it will start chopping with 50% duty cycle and the half period will be equal to the toff time set by the external components attached on pwm/ slew pin (#3). the fcom pin will continue to chop until the spindle outputs are disabled then it will go low. the table #6 shows the options of the fcom output signal available by the combination of the isns (reg#8.3), fll_out(reg#10.4) and mech/elec(reg#2.5) bits. table 6. fcom output signal 4.8 bemf rectification in case of a power down, at the falling edge of the por signal, the spindle outputs will be tristated and the retract sequence will initiate. the energy for the retract function in power down condition comes from the rectified bemf of the motor acting as a generator on vdd. because of the bottom spindle transistors are commutated in sync with the bemf, the voltage on vdd is only one diode drop less than the bemf voltage (the body diode of the top side spindle drivers). isns fll_out mech/elec fcom signal 0 0 0 toggle every zero crossing 0 1 0 toggle every mechanical turn 0 1 1 toggle every electrical turn 1 x x inductive sense
AN1138 application note 30/63 4.9 power stage the spindle power driver consist of a 3 phase h bridge power transistor. both the low and the high side drivers are nmos transistor. the drivers are built by a special low rdson dmos structure. the 12 volts power supply is connected to the h bridge via an external power nmos device. the h bridge returns to ground through the sink pins and via an external resistor. an on chip boost voltage generator is being used to switch the high side drivers and the external isolation nmos as explained in chapter 2 (auxiliary circuits), section 2.3 (charge pump). 4.10 external isofet an external nmos device is used to connect the power supply to the spindle and vcm high side dmos. the meaning of this device is to isolate the spindle and vcm power stage from the power supply during retract at power off. this will insure the bemf voltage available from the spindle motor to stay inside the chip and thus providing the necessary voltage to retract the voice coil. without this device, the bemf voltage will be dis- charged very fast through the power supply. the external isofet is turned on upon the por signal goes high and is turned off when the por signal goes low. the high voltage (~17v) to apply to the gate necessary to turn it on, it is provided by the charge pump circuit and it is available on sw1 pin (33). if no particular care is needed on the voltage drop of the external isofet, it can be substituted with a normal schottky diode. 4.11 external bemf processing option the external bemf processing is available by re-setting (=0) the reg#2.1 bit. at this time the fcom signal has to be monitored by the external m p as a zero crossing reference. upon the transition of the fcom signal, a se- quencer commutation needs to be programmed after a delay calculated by the m p itself. the delay has to be calculated as a percentage of the previous period (typical 30 electrical degree equal to half of the previous pe- riod). the mask time like in internal bemf processing is also calculated as a percentage of the previous period, but it is also performed by the high state of the commutation signal incre_seq (reg#2.0 bit). when the incre_seq bit is set (=1) the bemf is masked. the actual mask time signal is a combination of the two. the figure #19 in the chapter 6 (application and tools), section 6.1 (application configurations) depicts this feature. 4.12 external speed control option the external speed control is available through the fll_filter pin (21). by removing the components at- tached to this pin, the control of the input of the spindle ota can be reached by an external analog voltage signal (see figure #10). the feedback frequency for the external fll/pll can be taken from the fcom pin or from the data read off of the disk itself. during start-up, the ota input is internally forced high until the speed reach the value set by the internal fll counters, then the control is ended over to the charge pump leaving the fll_filter pin at high impedance. for this reason if the external speed control is chosen, the fll regis- ters has to be set to a lower speed than the target one. another way to perform the external speed control is through the serial port. this feature can be accomplished by turning on and off the cph and cpl bits (reg#8.6.7, see figure #10). in this case the external filter components are to be connected. the figure #20 in the chapter 6 (application & tools), section 6.1 (application configurations) depicts this feature.
31/63 AN1138 application note 5.0 voice coil circuits 5.1 description a complete voice coil control circuit plus 14 bit dac and dmos full bridge drivers are integrated in the chip. the class ab power stage which do not require snubber networks for load compensation, yet maintaining high accuracy on gain and offset parameter, allows a well controlled quiescent current, therefore maximum precision in the positioning of the head actuator. the reference voltage for the system is vdd/2 to allow symmetrical use of the available power supply. the dac command input to the actuator is a voltage centered around vdd/2 that swings 1v. 5.2 current control the current in the actuator is sensed by a small resistor (typ. 250m w ) in series to the coil. the voltage drop across the resistor is amplified by a differential amplifier with a gain of four. the output voltage of this amplifier is proportional to the current in the coil. this voltage and the dac voltage summed at the input of the error amplifier, represent the difference between the desired current and the actual motor current. the output of the error amplifier is the signal that will drive the power stage according to the driving mode selected. two dif- ferent modes are available, linear mode and phase shift modulation mode (psm). by changing the reg#0.6 bit, the selection of the two modes can be done any time regardless the voice coil motor is moving or not. the model and a mathcad analysis for the vcm current control loop can be found in chapter 8 (appendix), section 8.1.3 (voice coil current control loop). 5.2.1 linear control loop the linear control loop is selected by a 0 in the reg#0.6 bit. the complete system is described in figure #13. figure 13. voice coil linear control loop the loop consists of a 14 bit dac, error amplifier referenced to vdd/2, fixed gain (a=4) differential input current sense amplifier and positive and negative power output amplifiers (referenced to vdd/2). the output of the cur- rent sense amplifier (which is referenced to vdd/2) and the output of the dac are summed with external resis- tors at the input of the error amplifier. the error amplifier allows the bandwidth of the vcm to be compensated with an external rc filter and drives the positive and negative power amplifiers. the transconductance of the + + - - ri rf rc cc1 lm rs pin 37 sense_out pin 29 pin 27 sense_in+ sense_in- pin 26 pin 30 vcm_a+ vcm_a- pin 39 error_in error_out sense amplifier g=4 error amplifier a- a+ + - + - t1 t2 vdd/2 dac cc2 vx rm motor pin 38
AN1138 application note 32/63 loop formed by the error amplifier, power amplifiers and current sense amplifier is set by 4 times the value of the external current sense resistor (in series with the vcm), and the ratio of the two summing resistors ri and rf. the open loop bandwidth of the error amplifier is 10mhz with a gain of 100db. the open loop bandwidth of the power stage is 1mhz for a+ and 1mhz for a- with a gain of +8 for a+ and -8 for a-. therefore the total gain of the power stage is 16. the open loop bandwidth of the sense amplifier is 10mhz and the gain is set to 4. if the capacitor cc2 (figure #13) is choosen to be 10 times smaller than cc1, the pole created by cc2 is further reason the cc2 capacitor will not be included in the transfer function and the equation can be simplified as follow. ? 13. vcm loop transfer function the single pole response is independent from rc ( if set ). the bandwidth is set with cc1: ? 14. vcm loop bandwidth ? 15. vcm loop low frequency gain 5.2.2 psm control loop the psm control loop is selected by a 1 in the reg#0.6 bit. the complete system is described in figure #14. the architecture of the current sense, error amplifier and control voltage (from dac) are the same as for the linear mode of operation. however the output of the error amplifier (vx) is input to two comparators which switch the vcm+ and vcm- outputs on and off. figure 14. voice coil psm control loop i o v i ---- - r f grirs ------------------- 1 s rfcc1 rs rm + () 2agrs ----------------------------------------------- 1 + ? ?? ------------------------------------------------------------------ = cc1rc lm rs rm + ----------------------- = wo 2agrs rf rs rm + () cc1 ----------------------------------------------- = io vi ----- rf rigrs ------------------- = + + - - ri rf rc cc1 lm rs pin 37 sense_out pin 29 pin 27 sense_in+ sense_in- pin 26 pin 30 vcm_a+ vcm_a- pin 39 error_in error_out sense amplifier g=4 error amplifier a- a+ + - + - t1 t2 vdd/2 dac cc2 vx rm motor pin 38
33/63 AN1138 application note the second input of the two comparators is one of the two anti-phase triangle waves whose 50% voltage is vdd/2. as shown in figure #15, when the vx signal is equal to vdd/2, the outputs voltage vcm+ and vcm- are in phase (both high or both low) resulting zero current in the coil. when the vx signal is grater or less than vdd/2, the duty cycle of vcm+ and vcm- changes (if one increase the other decrease) resulting a positive or negative current into the coil. figure 15. voice coil psm output voltages & current signals the amplitude of the anti-phase triangle waves (t1,t2) has been chosen to keep the effective gain from vx to the output the same as in linear mode. this minimize transient dc shift in the control loop voltages when switch- ing between psm and linear modes. the frequency of the triangle waves is generated by an internal oscillator and its value is about 50khz +/- 30%. as can be noticed in figure #15, the effective chopping frequency is twice the frequency of the oscillator. 5.2.3 d/a converter a 14 bit dac is available through the serial port in the reg#0.0:5 (vcm dac high) and reg#1.0:7 (vcm dac low). it is required to write on register #1 to make effective changes on register #0. this means that if a change is done to a bit in a low vcm_dac register (bit 0 through bit 7), only the register #1 needs to be written. if a change is done to a bit in a high vcm_dac register (bit 8 through bit 13), both register #0 (first) and register #1 need to be written. the ladder of the dac and the dac circuit itself, are connected internally to a floating power supply in which a feedback system is keeping the supply centered to vdd/2. this is done mainly to compensate the variation of the power supply. the output of the dac swings from vdd/2 + 1v (dac set as hex.4000 or dec.16384) and vdd/2 -1v (dac set vcm- vcm+ output current current output vcm+ vcm- current vcm- output vcm+ vx > vcc/2 vx < vcc/2 vx = vcc/2
AN1138 application note 34/63 as hex.0 or dec.0). the zero current is set as vdd/2 (dac set as hex.2000 or dec.8192). the resolution volt- age (per lsb) is given by the full scale voltage (2v) divided by 14bit (16384) and it is equal to 122 m v. 5.3 retract the retract profile is set by the pkv_1, pkv_2 bits (reg #9.0.1), for parking voltage and rt0, rt1 bits for parking time (reg #9.3.6) in the serial port. because these bits are not reset by porb, they must be con- figured through the serial port after power-up. when programming retract time, the reg#8.2 bit must be always set to 0. tables #7 and #8 show respectively the retract voltage and retract time options. table 7. vcm retract voltage table 8. vcm retract time the retract sequence is initiated by a falling edge of porb or by a 0 to 1 transition on the retract bit (reg #9.7). figure #16 shows the vcm retract and spindle brake sequence at power off. figure 16. power off sequence the device offers the possibility to tristate or brake the voice coil outputs for half of the retract time selected. this allows more flexibility to the retract function. the tristate and brake bits are available respectively inside reg#11.5 and reg#11.6. pkv_1 pkv_2 retract voltage 0 0 0.850v 0 1 0.650v 1 0 1.600v 1 1 1.150v rt0 rt1 retract time 0 0 160ms 0 1 320ms 1 0 80ms 1 1 160ms vdd time retract brake 5v bemf rectification retract voltage reg#9.0.1 reg#9.3.6 retract time brake time capacitor por power on on pin#12 (brk_cap)
35/63 AN1138 application note 5.4 offset calibration a calibration mode can be enabled through the serial port by setting vcm_cal bit (reg#0.7) which allows the user to determine the offset of the sense amplifier. this is accomplished by enabling all of the vcm control cir- cuits except for the output drivers. this means that offset of the isense amplifier can be read directly on the vcm_cal pin (#22). the output offsets is calculated by programming zero current in the normal operation mode (vcm_cal bit=0) and measuring the output of the vcm_cal. by adjusting the dac bits, monitoring in the mean time the vcm_cal pin until the voltage on that pin reach the same value previously measured (when the vcm_cal bit was set (=1)), the dac value obtained will represent the real zero current reference. the vr bit (reg #9.2) needs to be set prior to start the offset calibration. this allow to reference the calibration amplifier to a very precise voltage (2v). the voltage on vcm_cal pin during calibration is 2v +/- offset. figure #17 shows the vcm calibration circuit. following is the step by step procedure to calibrate the voice coil offset. 1) enable voice coil circuits by setting vcm_en bit (=1) (reg#9.5). 2) apply a reference voltage to the calibration amplifier by setting vr bit (=1) (reg#9.2). 3) set vcm_cal bit (=1) (reg#0.7). control circuits are on but power drivers are off. 4) use an external adc to measure the voltage on pin vcm_cal as voffset . 5) reset vcm_cal bit (=0) (reg#0.7). 6) adjust dac output through vcm dac register (reg#0 and reg#1) until v(vcm_cal) =voffset . 7) save the dac value as a zero current reference. figure 17. voice coil offset calibration 5.5 power stage the voice coil is a class ab, h bridge type power driver with all power devices internal to the device. the h bridge consist of four nmos power transistor built by a special low rdson dmos power structure. the 12 volts power supply is connected to the h bridge via an external power nmos device. the h bridge returns to ground via vcm_gnd pin (28). pin 26 vcm_a- a- sense_in+ sense_in- sense amplifier - g=4 pin 37 sense_out + pin 29 pin 27 rf amplifier pin 39 ri error_in rc cc1 pin 38 + error_out error a+ vcm_a+ pin 30 - + amplifier calibration - vr dac vdd/2 vdd/2 pin 22 vcm_cal reg#9.2 lm rs 16k 16k 16k 16k cc2 vx rm motor
AN1138 application note 36/63 6.0 application & tools 6.1 application configurations altought the device offers the complete bemf processing and speed control loop inside, the possibility may exists where certain applications might require complete microprocessor control of those functions. the flexible architecture of this device give the m p the option to externally provide those features. the figure #18 depicts the stand alone configuration where the bemf processing and speed control loop are demanded to the power combo. in this case the m p has to provide the sysclk frequency and por signal has to be monitored for under voltage detection. fcom and the status register may also be monitored for fault condition. the registers have to be programmed once according to the desired bits configuration. figure 18. stand alone application configuration the figure #19, shows the external bemf processing configuration. in this case the fcom pin has to be con- tinuously monitored and the commutation signal has to be provided to index pin (#11). an explanation of this configuration setup can be found in chapter 4 (spindle circuits), section 4.11 (external bemf processing op- tion). power combo microprocessor or dsp sysclk sclk sdata 5v fcom spindle motor voice coil motor bemf processing speed control loop sden por
37/63 AN1138 application note figure 19. external bemf processing configuration the figure #20, shows the external speed control configuration. the feedback frequency is taken from the disk itself and the control voltage is entered on fll_filter pin (#21). an explanation of this configuration setup can be found in chapter 4 (spindle circuits), section 4.12 (external speed control option). figure 20. external speed control configuration the figure #21, shows both the external bemf processing and the speed control together in the same con- figurations. this option is the combination of the two features and it is illustrated in the explanation of the previ- ous figures #19 and figure #20. power combo microprocessor or dsp sysclk sclk sdata 5v fcom spindle motor voice coil motor bemf processing speed control loop sden por index pin power combo microprocessor or dsp sysclk sclk sdata 5v fcom spindle motor voice coil motor bemf processing speed control loop sden por fll_filter pin
AN1138 application note 38/63 figure 21. external bemf processing & speed control configuration 6.2 typical application in figure #22 is depicted a typical application circuit. the external components are selected to work with a 5400rpm spindle motor with inductance lm=1.2mh phase to phase and resistor rm=5.3 w phase to phase. the voice coil is assumed with an inductance lm=1.5mh and a resistor rm=13.3 w . the maximum spindle start-up current is set as vdd / (rm+2rdson+rsense) and it is equal to 1.85a with reg#8.4.5 bits set to 1. the vdd is equal to 5v. the maximum voice coil current is set to be 1a. since high current is demanded through the spindle and voice coil sense resistor, 1w power dissipation ca- pacity is recommended. if spindle linear current control loop is selected, the capacitor (3), attached to pwm/slew pin (#3) can be avoided. if spindle pwm current control loop is selected, the components, one resistor and one capacitor (4), attached to spin_comp pin (#44) can be avoided. the layers that goes from sense_in+ and sense_in- pins to the voice coil sense resistor must be at equal distance. a capacitor (1) connected to vdd and ground is required in order to clamp possible spike due to the current recirculation in the spindle windings. since the absolute maximum rating of the vdd (pin #13) line is 6v, precautions need to be taken in order not to allow the voltage on this pin to go above the limits. a recom- mended capacitor on vdd pin for a 5400rpm, two platters application is 22 m f tantalum type. this capacitor needs to be placed as closest as possible to the vdd pin (#13). also an under voltage on vdd can be very. this can happen for example during plug and unplug test of the drive power supply connector. it is indeed rec- ommended to use a protection circuit in order to better protect the supply lines. a good layout by separating the grounds will improve the noise immunity of the system. power combo microprocessor or dsp sysclk sclk sdata 5v fcom spindle motor voice coil motor bemf processing speed control loop sden por fll_filter pin index pin
39/63 AN1138 application note figure 22. typical application circuit 6.3 smart power development system (spds) the stmicroelectronics smart power development system is a family of hardware and software tools that are used with a personal computer to develop applications of smart power ics. using this tool engineers can quickly evaluate smart power ics and optimize their application designs obtaining the best possible performance and reliability in the shortest time. the spds is based on a ibm pc at compatible, as shown in figure #23. a pc interface board, suitable for any data transfer operation from or to the pc, is inserted into one pc isa expansion slot and interface the computer with the external devices. in addition, an evaluation board specific for one or more stmicroelectronics products, controlled by the spds software installed on the pc, provide the direct user application management. designed for one or more specific stmicroelectronics smart power products, the spds software provides a set of tools dedicated to the design development and optimization of applications which make use of the stmi- croelectronics smart power ics. spds software permits the evaluation and optimization of external compo- nents. spds software support the spds hardware and permits the driving of the application to test, modify and optimize in real time the application parameters. vdd 5v_vdd 5v_vdd vdd vdd vdd vcm_a- vcm_a+ ctap out_a out_b out_c 18.2k 1nf 0.25 ( 1w ) 62k 1uf 51k 5k (4) 62k 620k 2.2uf 0.3 ( 1w ) 10k 100nf + 16v 22uf + 16v 22uf 100nf 220pf ( 3 ) 100nf 10nf ( 4 ) 20k 4.7k 2n2222 1uf 10k 15pf 1ohm 20uh stn4ne03 tqfp44 5 13 21 24 23 32 36 28 3 12 19 35 40 33 44 11 14 39 41 38 20 22 16 17 18 31 15 34 1 37 29 27 30 26 4 7 10 2 25 9 42 43 6 8 isense vdd fll_filter cs cp fll_res por_delay vcm_gnd pwm/slew brk_cap vdd tr_5v clk_mon sw1 spn_comp index dgnd error_in dac error_out v5/2 vcm_cal sden sdata sclk vdd sys_clk porb fcom sense_out sense_in- sense_in+ vcm_a+ vcm_a- out_c out_b out_a ctap vdd rsense agnd vdd rsense gnd 1n4148 index sclk sden sys_clk fcom porb sdata voice coil ground power ground analog ground digital ground 10k (2) (1) (1) l6275
AN1138 application note 40/63 figure 23. smart power development system setup the spds tool for the devices described in this application note is available through the stmicroelectronics rep- resentative. 6.3.1 spds hardware the spds hardware consist of two boards, pc interface board (hwpci-st) and application board. the inter- face board provides a programmable interface between the pc and the external devices. inserted into one pc isa expansion slot , the board is memory-mapped: the pc reads/writes the expansion board as a common memory location. the interface board contains 4 eight-bit digital ports which can be programmed as outputs and/or inputs; a tim- ing section consisting of four general purpose counting/timing channels and one programmable rate generator channel is controlled by one 8mhz on-board crystal clock. the interface board is connected to the application board (external to the pc) with two flat cables. the applica- tion board is designed specifically for the devices depicted in this manual and provides all the external compo- nents necessary to the device itself. the figure #25 and figure #26 show the connection between interface and application boards. 6.3.1.1 interface board the interface card has a switch that defines the pc memory location in which it is allocated. the switch has to be set at hexcd00 address as explained in the figure #24. figure 24. spds interface board memory address, dip switch setting hwpci-st interface board l6275 board on off 12345678910
41/63 AN1138 application note the out0 pin of the jc1 jumper must be connected to irq5 pin of the jc2 jumper connector. the out1 pin of the jc1 jumper must be connected to irq3 pin of the jc2 jumper connector. this will allow the outputs of the timer0 and timer1 to generate an interrupt request respectively on irq5 and irq3 lines of the pc interrupt controller. the tgate3 pin must be connected to bgate3 pin of the gate jumper connector. the tgate1 pin must be connected to bgate1 pin of the gate jumper connector. this setting will allow the application board to control the counting of the timer1 and timer3. the timer 0 and 2 are enabled by software. the figure #25 shows the connectors and jumpers location. three connectors along with three flat cables interface the in- terface board with the external application board. connector c2 carries 16 bits input/output data through two 8 bits port, port 0 and port 1. connector c3 also carries 16 bits input/output data through port 2 and port 3. each port is configurable by software as input or output. the connector c3 is not utilized in the application of the devices depicted in this manual. connector c4 is the timer connector and carries the gate, clock and out signal for each of the four timer available on board. the rate generator output, which is programmable, is also available on connector c4. three 5v supply lines capable of 1a of current each isolated with fuses (fuse 1, fuse 2 and fuse 3) are avail- able on pin #34 of each cables. a detailed explanation of the interface card is available in a separate manual inside the spds tool box. important!!! the spds makes use of the irq3 and irq5 interrupt lines. if another board inside the pc is using the same lines, it is necessary to remove it to avoid the interrupt hardware conflit . figure 25. spds interface board, connectors and jumpers location 6.3.1.2 application board the application board is connected to the interface board with two flat cables. the port 0/1 cable, which provides all the digital input output signals, is connected between port 1 connector of the application board and connector c2 of the interface board. the timer cable, which provides the timings, is connected between timer connector of the application board and connector c4 of the interface board. two 5v supply lines available on pin #34 of port 1 and timer cables supply some of the application board ics. for this reason, please make sure that the fuses mounted on the interface board are working. an oscillator running at 20mhz required by the combo ic is available on board. a different frequency can be input at the bnc connector. the selection between on board and external frequencies is done by software. connector c2 connector c3 connector c4 port 0/1 port 2/3 timer gates jc1 jc2 dip switch to pc isa bus slot to / from application board port 1 to / from application board timer on off 0 1 2 3 0 1 2 3 bgate sgate out0 out1 out2 out3 irq2 irq3 irq4 irq5 irq6 irq7 12 3456 78910 fuse 3 fuse 2 fuse 1
AN1138 application note 42/63 figure 26. spds application board, connectors and jumpers location the supply to the board is provided through the supply connector. 5v is required. the spindle and the vcm are connected respectively to the spindle and voice coil connectors. a print on the pcb depicts the phases and polarity connection. four jumpers are available on board for evaluation purpose. jumper jp1 inserts a schottky diode between the vdd and the ics in case the isofet is not required. jp2 connects the input of the sense amplifier (isense) to the sense resistor (must be inserted). jp3 connects the vdd power supply to the voice coil section (must be inserted). jp4 connects the pc ground to the application board ground. a separate manual with a detailed schematic and explanation of the application board is avail- able inside the spds tool box. 6.3.2 spds software the smart power development system software is available on a 1.4m floppy disk. the diskette content is a number of files (7) that must be loaded and run from the fixed disk. it is suggested to set up a subdirectory for example spds and copy all the files into it. the software runs under dos environment and the following mod- ification needs to be done to the config.sys file. c:\...\emm386.exe noems x=cd00-cfc0 files=40 (or higher) buffers=40 (or higher) a file called readme.txt is include in the diskette, to read it use a common ascii editor. following is the directory of the files present on the floppy disk. st.bat starts the spds program lunching the logo.exe file logo.exe displays the stmicroelectronics logo mouse.exe installs the mouse driver spindle vcm 5v power supply 5v spindle voice coil port 1 timer supply to / from interface board connector c2 to / from interface board connector c4 bnc jp1 jp4 jp2 jp3
43/63 AN1138 application note mainm.exe spds application program tmsrb.fon spds fonts lastfile.spd contains spds program macro routine readme.txt contains spds setup information the source files of the spds program are also available upon request, please ask a stmicroelectronics repre- sentative. to start the program simply type st and press enter . after the st logo is displayed, type any key to enter the spds environment. following in figure #27 is the real-time frame of the spds environment. figure 27. spds software realtime frame the spds software is completely accessible through a mouse and/or keyboard. using the mouse, move the pointer to the desired location on the screen. the pointer shape will change from an arrow to a little hand, then press the left button. using the keyboard, an under lined letter determines the short key to enter the function. where the under lined letter is not available, use the tab key to move between the parameters. use arrow up and down keys to change the parameters value. a separate dedicated manual with a detailed explanation of the spds software is available inside the spds tool box. previous window exit to dos device and software informations load macro routines save macro routines open hardware and device registers window open realtime window open spindle speed profile window edit macro routines change parameters up & down reset device and sofware execute macro routines system keys voice coil realtime section spindle realtime section active window device status section device thermal section device registers and bits section device in use product line file in use system clock in use resolution in use interface card check interface timer check device por check interrupt request in use close current window l6275 a569
AN1138 application note 44/63 7.0 package & thermal 7.1 tqfp44 package the device is mounted in a thin quad flat 44 pin package (tqfp44). the dimensions of the body are 10x10x1.40mm. the mounting information are outlined in the following figure #28. figure 28. tqfp44 dimensions tqfp44 (10 x 10) dim. mm inch min. typ. max. min. typ. max. a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.30 0.37 0.45 0.012 0.014 0.018 c 0.09 0.20 0.004 0.008 d 12.00 0.472 d1 10.00 0.394 d3 8.00 0.315 e 0.80 0.031 e 12.00 0.472 e1 10.00 0.394 e3 8.00 0.315 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 k 0 (min.), 3.5?(typ.), 7 (max.) a a2 a1 b seating plane c 11 12 22 23 33 34 44 e1 e d1 d e 1 k b tqfp4410 l 0.10mm .004 outline and mechanical data
45/63 AN1138 application note 7.2 thermal characteristics the thermal characteristics are influenced by many factors. these can not be described by a single thermal re- sistance, in fact a set of experimental curves gives the best presentation. two thermal resistance are more im- portant, the junction to ambient thermal resistance, rthj-a, and the junction to case thermal resistance, rthj-c. rthj-a, represents the thermal resistance of the system and comprises the silicon die, the package, and any thermal mass in contact with the package to dissipate heat to the ambient. at a given dissipation level pd, the increase in junction temperature d tj over ambient temperature ta is given by: d tj = rthj-a * pd. rthj-a is made up for many elements both within the device and external to it. if the device is considered alone, rthj-a is given by the dissipation path from the silicon die to the lead frame, to the molding compound. the rthj- a for the tqfp44 package is 40 to 45 c/w. the figure #29 shows the equivalent thermal circuit simplified. figure 29. equivalent thermal circuit simplified package rthj-c, is the thermal resistance from the junction to a give area of the packages external surface. the junction to top case thermal resistance for this package is 11 c/w. however this value is obtained in an extreme envi- ronment where 100% of the heat is dissipated through package top case. in the application environment, only less than 10% of the heat is dissipated through this path. therefore, tj should be calculated in the following way: ? 16. junction temperature this gives tj ~ tc + pd. hence the junction temperature is only slightly higher than the case temperature. example with : n multilayer printed circuit board: 4 layers. n board size: 10x10cm l shaped. n die size: 20mm 2 n dissipating area: 20mm 2 n spindle spin-up: 2w for 3sec. n average power dissipation. spindle + vcm: 0.5w according to this condition, the thermal resistance junction to ambient should be around 42-45c/w (with- out any forced air flow). if the board is mounted in some metal enclosure, this can help to remove the heat re- ducing the rthj-a to 35-40c/w (provided that there is enough space around the package to have an almost t j tamb rth rth rth silicon frame mold rth cth cth cth silicon frame mold t j t c 10% p d r thj c C () + =
AN1138 application note 46/63 free air convention flow). in steady state condition (stable running dissipation spindle + vcm) the junction temperature increase is in the range of 20-25c maximum. for the transient behaviour, up to 3 seconds (spindle spin-up) the board dimension are not so important as, within this time, almost all the heat is still inside the package. in this case the key parameters to identify the transient thermal impedance are the die size, the dissipating area, the package geometry. under the condition of this example, the thermal impedance @3sec is about 18c/w. this means tha at 3 seconds of spin -up, the temperature increase is between 35 to 40c. in conclusion, the spin-up phase induces a temperature increase for the junction of about 35-40c; after that when the steady state running will take place the junction temperature will go down and will stabilize around 20-25c. to have the absolute junction temperature, simply add the ambient temperature. 7.3 slug the device provides a piece of metal (slug) mounted on the back of the package. this metal, melted in the plastic of the package is designed to handle higher power dissipation by lowering the junction to ambient ther- mal resistance. when the slug is soldered to the pcb, the rthj-a is 30 to 35c/w. following in figure #30 is outlined the slug dimension. figure 30. tqfp with slug, package outline the figure #31 shows rhe suggested pattern to sold the device slug to the drive board. figure #32 depicts the design and dimension of the slug mounted on the back of the tqfp44 package. figure #33 shows the device temperature rise with and without slug. dimensions tolerances lead count (mm) 44 64 amax. 1.60 a1 +/-0.05 0.10 a2 +/-0.05 1.40 d +/-0.20 12.00 d1 +/-0.10 10.00 d3 typ. 8.00 7.50 e +/-0.20 12.00 e1 +/-0.10 10.00 e3 typ. 8.00 7.50 l +/-0.15 0.60 l1 typ. 1.00 e t yp. 0.80 0.50 b +/-0.05 0.35 0.23 cmax. 0.20 s1 typ. 6.00 s2 typ. 6.00 htyp. 5.90 k(deg.) 0-7 e3 e1 e d3 d1 d l l1 b a a2 a1 s1 s2 h c
47/63 AN1138 application note figure 31. raccomended pattern for slug soldering to pcb figure 32. tqfp slug design figure 33. ic temperature crise b a package sizes a b 10x10x1.4mm 2.00 mm 1.00 mm copper slug d/a glue (thick. = 30 ) die thickness : 375 +/- 25 lead frame 1.60 mm max. solder plated spot ag plated 0.10 mm +/- 0.05 0 1020304050 time ( sec ) 0 20 40 60 80 100 120 junction temperature rise (c) 0 1 2 3 4 5 6 full plastic slu g slu g soldered on pcb 94 53 72.5 power (w) power
AN1138 application note 48/63 8.0 appendix 8.1 models & mathcad analisys following are the models and mathcad analisys for the spindle current control loop, spindle speed control loop and voice coil current control loop. the external component used are referred to the typical application depict- ed in figure #22. the 5.0 release of mathcad has been used and a floppy disk with the three analisys is available through the stmicroelectronics representative. 8.1.1 spindle current control loop figure #34 shows the spindle current control loop model used for the analisys. figures 35a, 35b, 35c show the mathcad analisys of the loop. figure 34. spindle current control loop model gm2 fll gm1 ro1 rc cc x1 rota x1 cm1 ra cgd cgs ro2 cds lm rm rs x4 (user specified parameters) rc . 510 3 (external compensation resistance) cc . 10 10 9 (external compensation capacitance) rm 5.3 (motor's windin g resistance - phase to phase) lm . 1.2 10 3 (motor's windin g inductance - phase to phase) rs 0.3 (external sense resistor) (device parameters) gm1 . 0.6 10 3 (transconductance of ota) ro1 . 5.3 10 6 (output resistance of ota) rota . 10 10 3 (output resistance of ota buffer) cml . 20 10 12 (miller capacitor value) ra 130 (output resistance of predriver) id . 110 10 3 (coil current) gm2 . 2.7 id (transconductance of dmos) = gm2 0.895 ro2 5.2 id (output resistance of dmos) = ro2 47.273 cds . 30 10 12 (drain-source capacitance of dmos) cgd . 12 10 12 (gate-drain capacitance of dmos ) cgs . 30 10 12 (gate-source capacitance of dmos ) a4 (gain of sense amplifier)
49/63 AN1138 application note figure 35a. mathcad analisys of the spindle current control loop 1st stage (ota) transfer function : a1 . gm1 ro1 = a1 3.18 10 3 wz 1 . rc cc fz wz . 2 p = fz 3.183 10 3 wp 1 . cc ( ) rc ro1 fp wp . 2 p = fp 3 g( ) s . a1 1 s wz 1 s wp ( transfer function of ota after compensation) 2nd stage transfer function : i 1 f( ) n10 n s( ) n . . . 2i p 10 n n.. , 1 1.01 6 zl( ) n . lm s( ) nrm (motor) h1( ) n . a1 1 s( ) n wz 1 s( ) n wp (ota) ci cgs cgd co cgd cds h2( ) n 1 ra . ci s( ) n () . cgd s( ) ngm2 () . cgs s( ) ngm2 0 . cgd s( ) n . () cml co s( ) n 1 ro2 1 zl( ) n 1 ro2 . cds s( ) n . cml s( ) n 0 0 0 1 rota 1 ra . cml s( ) n 0 1 rota . cml s( ) n 1 ra . ci s( ) n () . cgd s( ) ngm2 () . cgs s( ) ngm2 0 . cgd s( ) n . () cml co s( ) n 1 ro2 1 zl( ) n 1 ro2 . cds s( ) n . cml s( ) n . cgs s( ) n gm2 1 ro2 . cds s( ) n . () cgs cds s( ) ngm2 1 ro2 1 rs 0 1 ra . cml s( ) n 0 1 rota . cml s( ) n
AN1138 application note 50/63 figure 35b. mathcad analisys of the spindle current control loop open loop response h( ) n . h1( ) nh2() n= h( ) 0 584.28 magnitude response in db 10 100 1000 1 10 4 1 10 5 1 10 6 50 40 30 20 10 0 10 20 30 40 50 0 . 20 log( ) h( ) n f( ) n phase response in degrees 10 100 1000 1 10 4 1 10 5 1 10 6 180 140 100 60 20 20 60 100 140 180 . arg( ) h( ) n 360 . 2 p f( ) n
51/63 AN1138 application note figure 35c. mathcad analisys of the spindle current control loop close loop response cl( ) n h( ) n 1 . ah( ) n magnitude response in db 10 100 1000 1 10 4 1 10 5 1 10 6 50 40 30 20 10 0 10 20 30 40 50 0 . 20 log( ) cl( ) n f( ) n phase response in degrees 10 100 1000 1 10 4 1 10 5 1 10 6 180 120 60 0 60 120 180 . arg( ) cl( ) n 360 . 2 p f( ) n
AN1138 application note 52/63 8.1.2 spindle speed control loop figure #36 shows the spindle speed control loop model used for the analisys. figures 37a, 37b, 37c show the mathcad analisys of the loop. figure 36. spindle speed control loop ifll fref fref 1 asrs gm zfilter km s*jm 2*pi 1 rc cc1 cc2 fm fref 90 reference clock frequency(hz) speed at 5400rpm kfll 1 *charge pump current gain(1or4) ifll . . 25 10 6 kfll charge pump current(a) = ifll 2.5 10 5 as 4 *sense amp gain rs . 310 1 *sense resistor(0.3ohms) gm 1 . as rs current loop transconductance(a/v) = gm 0.833 km 125 *motor torfque constant(gm-cm/a) jm 0.2 *motor inertia(gm-cm-sec-sec) rc . 0.43 10 6 *fll compensation resistor cc1 . 110 6 *fll compensation capacitor cc2 . 0.1 10 6 *fll compensation capacitor
53/63 AN1138 application note figure 37a. mathcad analisys of the spindle speed control loop velocity loop transfer function : i 1 f( ) n10 n s( ) n . . . 2i p 10 n n.. , 2 1.99 3 sz 1 . rc cc1 filter zero fz sz . 2 p = fz 0.37 sp 1 . rc . cc1 cc2 cc1 cc2 filter p ole fp sp . 2 p = fp 4.071 kc 1 cc1 cc2 zfilter( ) n . kc s( ) n sz 1 . s( ) n s( ) n sp 1
AN1138 application note 54/63 figure 37b. mathcad analisys of the spindle speed control loop open loop gain h( ) n . . . . ifll fref zfilter( ) ngm km . jm s( ) n 1 . 2 p let k . . . ifll fref gm jm km . 2 p kc = k 20.933 open loop magnitude response in db 0.01 0.1 1 10 100 1000 50 40 30 20 10 0 10 20 30 40 50 . 20 log( ) h( ) n f( ) n open loop phase response in de g ree 0.01 0.1 1 10 100 1000 180 170 160 150 140 130 120 110 100 90 . arg( ) h( ) n 360 . 2 p f( ) n
55/63 AN1138 application note figure 37c. mathcad analisys of the spindle speed control loop close loop gain c( ) n h( ) n 1h() n close loop magnitude response in db 0.01 0.1 1 10 100 1000 50 40 30 20 10 0 10 20 30 40 50 . 20 log( ) c( ) n f( ) n close loop phase response in de g rees 0.01 0.1 1 10 100 1000 180 135 90 45 0 45 90 135 180 . arg( ) c( ) n 360 . 2 p f( ) n
AN1138 application note 56/63 8.1.3 voice coil current control loop figure #38 shows the voice control loop model used for the analisys. figures 39a, 39b, 39c show the mathcad analisys of the loop. figure 38. voice coil current control loop model dac lm rm rs cc2 cc1 rc rf wota wamp ri kamp=16 ksen=4 device parameters kamp 16 gain of power stage wamp . 600 10 3 pole of power stage ksen 4 gain of sense amplifier wota . 60 10 6 pole of ota user specified value lm . 1.5 10 3 coil inductance rm 13.3 coil resistance rs 0.25 sense resistance ri . 110 4 input resistor kgm 1 target dc loop transconductance(a/v) rf . 110 4 feedback resistor suggested rf value rfs . . . ksen rs ri kgm = rfs 1 10 4 bw . 110 4 target bandwidth(hz) cc1 . 1.8 10 9 compensation capacitance suggested cc1 value cc1s . . ksen rs kamp . . . . rf ( ) rs rm 2 p bw = cc1s 1.879 10 9 cc2 . 1.8 10 10 compensation capacitance suggested cc2 value cc2s cc1 10 = cc2s 1.8 10 10 rc . 6.2 10 4 compensation resistance suggested rc value rcs lm . cc1 ( ) rs rm = rcs 6.15 10 4
57/63 AN1138 application note figure 39a. mathcad analisys of the voice coil current loop i 1 f( ) n10 n s( ) n . . . 2i p 10 n n.. , 1 1.01 6 kc 1 . () cc1 cc2 ri = kc 5.051 10 4 wz 1 . rc cc1 fz wz . 2 p = fz 1.426 10 3 wp 1 . rc . cc1 cc2 cc1 cc2 fp wp . 2 p = fp 1.569 10 4 h1( ) n . kc 1 s( ) n wz . . 1 s( ) n wota 1 s( ) n wp s( ) n compensator h2( ) n kamp 1 s( ) n wamp power sta g e h3( ) n 1 . lm s( ) nrmrs fl rm rs . . 2 p lm = fl 1.438 10 3
AN1138 application note 58/63 figure 39b. mathcad analisys of the voice coil current loop open loop response h( ) n . . h1( ) nh2() nh3() n= h( ) 1 949.152 magnitude response in db 10 100 1000 1 10 4 1 10 5 1 10 6 50 40 30 20 10 0 10 20 30 40 50 0 . 20 log( ) h( ) n f( ) n phase response in degrees 140 100 60 20 20 60 100 140 180 . arg( ) h( ) n 360 . 2 p
59/63 AN1138 application note figure 39c. mathcad analisys of the voice coil current loop close loop response a . . ksen rs ri rf = a1 cl( ) n h( ) n 1 . ah( ) n = . 20 log( ) cl( ) 1 1.464 10 6 magnitude response in db 10 100 1000 1 10 4 1 10 5 1 10 6 25 20 15 10 5 0 5 10 15 20 25 0 . 20 log ( ) cl( ) n f( ) n phase response in degrees 10 100 1000 1 10 4 1 10 5 1 10 6 180 120 60 0 60 120 180 . arg( ) cl( ) n 360 . 2 p f ( ) n
AN1138 application note 60/63 8.2 state diagram the figure #40 depicts the complete spindle motor controller state diagram. this include, internal align & go start-up, external start-up and resynchronization. figure 40. spindle motor controller state diagram por=0 run=1 fr om a ny s tate be m f! run=0 fr om an y s ta te period count out_ena=1 loa d delay = min loa d mask =m in res e t pe riod period count delay count * p hase=ph as e+1 ma sk count bemf drivers on loa d delay = per iod loa d mask =p erio d res e t pe riod period count delay count * p hase=ph as e+1 ma sk count bemf be m f driv ers on go=0 align =0 perio d s top delay stop mask stop stkrtr=0 (4 20 m s ) ph ase=ph ase +2 alig n= 1 (12 8m s) p hase=ph as e+1 loa d delay = min loa d mask =m ax period count delay count p hase=ph as e+1 ma sk count go = 1 (3 84 m s ) stkrtr=0 (4 20 m s ) be m f! be m f phase=1 drivers off min clock delay period stop d e la y s top ma sk stop driv ers off lo ad m in de la y lo a d m i n m a s k perio d s top de la y co un t pha se=p has e+1 mask co unt m in cloc k delay * cloc k de la y = f (td ly _ [3 :0] ) w he n bem f per iod < 3. 3 m s @ 20 m h z (speed > 1 2.7h z f or 8 p oles) go=1 align=1 go=1 align =1 pha se=p has e+2 out_e na=0 driv ers off drivers off go=1 p hase=ph as e+1 min clock delay load min delay loa d max mask delay count p hase=ph as e+1 ma sk count out_ena=0 out_e na=1 out_ena=0 out_ena=0 out_ena=0 out_ena=1 lo ad min delay out_ena=1 bemf bemf align & go m ode res ync hr onization mode bemf : bem f rising with pnslope=1 or bemf falling with pnslope=0 bemf! : bemf rising with pnslope=0 or bem f falling with pnslope=1 ** g tm o no = 0 w h en fr e q(b em f)= 2 *fr e q( ph a s e ) ru n= 0 ru n mode ru n= 1 & out_ena=1 outext=0 min clock delay =200ns period min m ask = 19 .2 us max mask = 3.27 ms drivers off m in clock delay period stop (420 ms) stkr tr = 0 min delay = 600ns- 9us (f(tdly[3:0])) internal start up disabled load min m ask lo ad m in de la y pe rio d c o un t de la y c oun t mask co unt drivers off out_ena=0 out_ena=1 bemf zc = b emf load d elay = perio d load m ask=p eriod reset per io d pe r iod c o un t delay count mask co unt bemf m asked dr iver s on pe r iod c ou nt delay count mask co unt load min mask delay count p hase=p has e+1 mask count ph ase=ph as e+1 outext=1 se qinc = 1 seq i nc = 0 be m f seq i nc = 1 seqinc=1 seqinc=0 outext=0 seqinc=0 outext=1 ou te xt= 1 outext=0 seqinc=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . extern al mode bemf m asked ph ase=ph as e+1
61/63 AN1138 application note 8.3 inductive sense start-up step by step following is the step by step approch to perform the inductive sense start-up option. the device has to be programmed exactely in the order described. a flow chart of this start-up is available in figure #4 inside chaper 4 (spindle circuits) in section 4.1.2.3 (inductive sense). general setup 1. incre_seq - reg#2.0 [transition 0 to 1 increments spindle sequencer ]. set to 0 . 2. start_up - reg#2.1 [1 = internal start-up, 0 = external]. set to 0 . 3. r_seq - reg#2.2 [1 = reset sequencer to phase 1]. set to 1 . 4. r_seq - reg#2.2 [1 = reset sequencer to phase 1]. set to 0 . 5. run - reg#2.3 [1 = start internal align&go start-up, 0 = reset logic]. set to 0 . 6. spin_en - reg#2.4 [1 = enable spindle outputs, 0 = disable]. set to 0 . 7. ext/int - reg#2.7 [1 = external spindle feedback ,0 = internal]. set to 1 . 8. mec/elec - reg#2.5 [1 = electrical cycle for fll, 0 = mechanical]. set as required . 9. 8_12_pole - reg#3.3 [1 = 8 pole, 0 = 12 pole]. set as required . 10. icp - reg#8.1 [1 = 25 m a, 0 = 100 m a ]. set as required . 11. pwm/lin - reg#2.6 [1 = pwm current control, 0 = linear ]. set to 1 . 12. fll , fine and coarse counters - regs# 4,5,6. set as required . 13. isns - reg#8.3 [1 = presets spindle inductive start-up sense circuits]. set to 1 . 15. run - reg#2.3 [1 = start internal align&go, 0 = reset logic]. set to 1. phase detection 16. set trial counter to 1. 17. set phase counter to 1. 18. preset a counter with at least 500ns resolution. 19. store initilal time period. 20. spin_en - reg#2.4 [1 = enable spindle output, 0 = disable]. set to 1. 21. start counter . 22. monitor at the same time, the fcom pin #1 output for transition from low level (0 volt) to high level (5 volt) and the counter for the end of count (>50ms). 23. if counter is greater than 50ms, set to 0 spin_en reg#2.4 and lower the threshold according to step #14. then restart from step # 16. 24. if the threshold is reached ( fcom is at high level), stop counter and reset to 0 spin_en - reg#2.4 bit. 25. if counter time is shortest than the previous one, store time and phase . 26. incre_seq - reg#2.0 [transition 0 to 1 increments spindle sequencer]. set to 1 . 27. incre_seq - reg#2.0 [transition 0 to 1 increments spindle sequencer]. set to 0 . 28. increment phase and reapet from step #20 until phase =6. 29. store phase with lowest time. 30. increment trial and repeat from step # 19 until trial =5.
AN1138 application note 62/63 31. get the phase with a most frequent lowest time. ( phase is a position where the rotor is suppose to be). starting 32. isns - reg# 8.3 [1 = preset spindle inductive start-up sense circuits]. set to 0 . 33. pwm/lin - reg#2.6 [1 = pwm current control, 0 = linear ]. set as required . 34. il1/il0 - reg#8.4.5 [phase detection current threshold]. set as required . 35. r_seq - reg#2.2 [1 = reset sequencer to phase 1]. set to 1 . 36. r_seq - reg#2.2 [1 = reset sequencer to phase 1]. set to 0 . 37. if phase =1 go to step # 41. 38. incre_seq - reg#2.0 [transition 0 to 1 increments spindle sequencer]. set to 1 . 39. incre_seq - reg#2.0 [transition 0 to 1 increments spindle sequencer]. set to 0 . 40. repeat from step # 38 for phase minus 1 times. (example: if phase =3 repeat 2 times. this is to bring the sequencer to the same phase of the rotor). 41. spin_en - reg#2.4 [1 = enable spindle outputs, 0 = disable]. set to 1 . 42. start_up - reg#2.1 [1 = internal start-up, 0 = external]. set to 1 . 43. wait 10ms (this time may vary). 44. start_up - reg#2.1 [1 = internal start-up, 0 = external]. set to 0 . (steps # 42, #43, #44 are to charge the external compensation capacitor if linear mode is used. if pwm mode is used, they may be skipped). 45. incre_seq - reg#2.0 [transition 0 to 1 increments spindle sequencer]. set to 1 . 46. incre_seq - reg#2.0 [transition 0 to 1 increments spindle sequencer]. set to 0 . 47. wait 20ms (this time may vary). 48. incre_seq - reg#2.0 [transition 0 to 1 increments spindle sequencer]. set to 1 . 49. incre_seq - reg#2.0 [transition 0 to 1 increments spindle sequencer]. set to 0 . 50. wait 3ms (this time may vary). 51. start_up - reg#2.1 [1 = internal start-up, 0 = external]. set to 1 . 52. check for desired speed . 53. sd0...sd3 - reg#3.7.6.5.4. [commutation delay]. set as required
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics a 1999 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the neth erlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. http://www.st.com 63/63 AN1138 application note

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